1. Field of the Invention
The present invention relates to a semiconductor device and a method of controlling the same.
Priority is claimed on Japanese Patent Application No. 2009-218819, filed Sep. 24, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, a reduction in chip costs of general-purpose DRAM has been required, and miniaturization of DRAM elements has progressed. A DRAM memory cell includes a transistor and a capacitor. Therefore, the miniaturization of DRAM elements is likely to cause a decrease in capacitance and an increase in leak current of a transistor.
For this reason, next generation memory, such as MRAM (Magnetic RAM), PCM (Phase Change Memory), and FeRAM (Ferroelectric RAM), has been developed to replace DRAM. Additionally, capacitorless memory has attracted attention as a next generation memory device. The capacitorless memory has a simple structure utilizing a floating body effect, which is observed in SOI (Silicon On Insulator) devices.
In related art, memory using the floating body effect (hereinafter, “floating body memory”) uses, for a memory operation, a difference in threshold voltage of a transistor, which is caused by a difference in the amount of holes stored in the body (see Japanese Patent Laid-Open Publication No. 2003-68877). However, the difference in threshold voltage between a “0” state and a “1” state is small, and thereby causes unstable operations.
For this reason, a method of using the bipolar current has been proposed in order to increase the difference in threshold voltage between a “0” state and a “1” state (see International Publication No. WO 2007/028583 A1). As a method of stabilizing operations of the floating body memory, nodes of two transistors are shared and connected in series in one memory cell (see International Publication No. WO 2005/122244 A1).
As a technique related to floating body memory, there has been provided a method of providing, on a gate of an HVFET (high-voltage field-effect transistor), a potential distribution such that the absolute value increases as a point comes closer to the drain (see Japanese Patent Laid-Open Publication No. 2005-277377). There has been provided a method of forming a nonvolatile semiconductor memory device including three-dimensionally stacked memory cells (see Japanese Patent Laid-Open Publication No. 2008-72051).
However, a relatively high voltage is required for bipolar operation of a transistor. For this reason, application of the bipolar operation to low-power-consumption DRAM has been difficult. The electrostatic capacitance of a body of the floating body memory, which stores an electric charge, is much smaller than the electrostatic capacitance of a capacitor of DRAM of the related art. For this reason, with the miniaturization of the floating body memory, it has been difficult to increase a data holding time and to enhance the refresh characteristics.
Further, the width of the body region has to be increased in order to increase the data holding time, and therefore the base length during the bipolar operation has to be increased. For this reason, an on-state current decreases, thereby causing an unstable operation.
Moreover, the method of connecting two transistors in series in one memory cell causes an increase in the occupied area of a transistor. For this reason, the occupied area of the memory cell increases, thereby making it difficult to form high-integrated DRAM elements.